std1364 verilog std

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Abstract: The Verilog® Hardware Description Language (HDL) is defined in this standard.

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Introduction
The Verilog® Hardware Description Language (Verilog HDL) became an IEEE standard in 1995 as IEEEStd 1364-1995. It was designed to be simple, intuitive, and effective at multiple levels of abstraction in a standard textual format for a variety of design tools, including verification simulation, timing analysis, test analysis, and synthesis. It is because of these rich features that Verilog has been accepted to be the language of choice by an overwhelming number of IC designers.

Verilog contains a rich set of built-in primitives, including logic gates, user-definable primitives, switches, and wired logic.

The mixing of abstract levels is essentially provided by the semantics of two data types: nets and variables.

The Verilog language is extensible via the Programming Language Interface (PLI) and the Verilog Procedural Interface (VPI) routines

The language that influenced Verilog HDL the most was HILO-2, which was developed at Brunel University in England under a contract to produce a test generation system for the British Ministry of Defense

Objective of the IEEE Std 1364-2001 effort

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Achievements
Over a period of four years the 1364 Verilog Standards Group (VSG) has produced five drafts of the LRM.

Three new sections have been added. Clause 13, “Configuring the contents of a design,” deals with configuration management and has been added to facilitate both the sharing of Verilog designs between designers and/or design groups and the repeatability of the exact contents of a given simulation session.

Extreme care has been taken to enhance the VPI routines to handle all the enhancements in the Behavioral and other areas of the LRM.

The IEEE Std 1364-2001 Verilog Standards Group organization

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1. Overview
1.1 Objectives of this standard
1.2 Conventions used in this standard