std 1800 system verilog

Abstract: This standard provides a set of extensions to the IEEE 1364™ Verilog® hardware
description language (HDL) to aid in the creation and verification of abstract architectural level
models.

(page iii)
Introduction
The purpose of this standard is to provide the electronic design automation (EDA), semiconductor, and system design communities with a well-defined and official IEEE unified hardware design, specification, and verification standard language. The language is designed to coexist and enhance the hardware description languages (HDLs) presently used by designers while providing the capabilities lacking in those languages.

Introduction
The purpose of this standard is to provide the electronic design automation (EDA), semiconductor, and system design communities with a well-defined and official IEEE unified hardware design, specification, and verification standard language
(Comments: S-verilog is meant to be a complement to verilog)

SystemVerilog is a unified hardware design, specification, and verification language that is based on the Accellera SystemVerilog 3.1a extensions to the Verilog HDL [B1]a, published in 2004.


(page 5)
SystemVerilog enables the use of a unified language for abstract and detailed specification of the design, specification of assertions, coverage, and testbench verification that is based on manual or automatic methodologies

(page 17)
1. Overview
1.1 Scope
This standard specifies extensions for a higher level of abstraction for modeling and verification with the Verilog® hardware description language (HDL).

1.2 Purpose
SystemVerilog is built on top of IEEE Std 1364.

(page 18)
SystemVerilog adds extended and new constructs to Verilog, including the following Extensions to data types for better encapsulation and compactness of code and for tighter specification Extended operators for concise description
Extended procedural statements
Enhanced process control